In recent years, with increase in data rate due to migration of communication systems to broadband, discrete-time circuit realization, which converts an analog circuit to a digital circuit to facilitate circuit design, has been advancing. Furthermore, concurrently with this, reduction in operating voltage has been expedited associated with miniaturization of a process to be used.
Therefore, for an A/D (analog-digital) converter, there has been the necessity to improve an SNR (Signal to Noise Ratio) characteristic and to realize lower voltage in a circuit. Also for a quantizer included in an A/D converter, there has been the necessity to realize a multibit configuration at the time of a low voltage operation.
FIG. 8 is a circuit diagram illustrating an example of a conventional delta sigma A/D (analog-digital) modulator described in Patent Literature 1, which is capable of realizing lower voltage in a multibit quantizer.
The delta sigma A/D modulator illustrated in FIG. 8 is a tracking mode delta sigma A/D modulator, and includes: a DAC circuit (digital-analog conversion circuit) 101; an integration circuit 102 for integrating a value obtained by adding (subtracting) an output signal of the DAC circuit 101 to (from) an input analog signal; a multibit quantizer 103 that has n (n is an integer of 2 or more) comparators 107-1 to 107-n, and that quantizes an output signal of the integration circuit 102, thereby outputting a digital signal; a logic processing circuit 104 for processing the digital signal outputted from the quantizer 103, thereby generating output digital data; a reference voltage generation circuit 105 for generating m (m is an integer greater than n) reference voltages VR-1 to VR-m for quantization, which are outputted to the quantizer 103; and a DAC control circuit 106 for receiving, as an input, the output digital data generated by the logic processing circuit 104, and for controlling the level of the output signal of the DAC circuit 101.
The n comparators 107-1 to 107-n, constituting the quantizer 103, each have one input terminal to which the output signal of the integration circuit 102 is inputted, and the other input terminal to which a different one of reference voltages VR1 to VRn is inputted. Output signals of the comparators 107-1 to 107-n are each inputted to the logic processing circuit 104.
The logic processing circuit 104 controls, based on the digital signal outputted from the quantizer 103, a reference signal (voltage) outputted from the reference voltage generation circuit 105, and synthesizes and outputs the output digital data as an output signal of the delta sigma A/D modulator as described above.
In the configuration of FIG. 8 in particular, based on the digital signals outputted from the n comparators 107-1 to 107-n for each sampling time, and a control signal value outputted to the reference voltage generation circuit 105 at the preceding sampling time, the logic processing circuit 104 outputs, at the next sampling time, a control signal to the reference voltage generation circuit 105 that outputs reference voltages in a switchable manner, and calculates and outputs digital data that should be outputted from the delta sigma A/D modulator.
In this case, from among the m reference voltages VR-1 to VR-m outputted from the reference voltage generation circuit 105, the n reference voltages are selected in advance as the reference voltages VR1 to VRn at the preceding sampling time, and supplied to the quantizer 103 including the n comparators 107-1 to 107-n, so that the output signal of the integration circuit 102 can be always determined within a determinable range in which the signal level thereof can be determined without saturation. The logic processing circuit 104 performs this selection by a control method set in advance.
Eventually, the tracking mode delta sigma A/D modulator configured as illustrated in FIG. 8 has a comparator configuration including the n comparators; whereas, as the reference voltages VR1 to VRn for comparison supplied to the n comparators 107-1 to 107-n, the n reference voltages are selected from the m (n<m) reference voltages VR-1 to VR-m, the number of which is larger than that of the comparators, and are supplied to the quantizer 103, thereby enabling comparative determination and digital output of the signal inputted from the integration circuit 102. Therefore, the digital output data for the number of steps m (log2 (m+1) bits) equal to the number of the actually switched reference voltages can be outputted from the logic processing circuit 104.
Thus, when a delta sigma A/D modulator for the number of steps m is implemented, m comparators are required in a configuration using no tracking mode; whereas, in the configuration of FIG. 8, the delta sigma A/D modulator for the number of steps m can be implemented with the n comparators. In other words, the number of comparators can be reduced by the number (m-n), thereby providing effective means for reducing circuit area and current consumption.